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Analog testability analysis and fault diagnosis using behavioral modeling

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4 Author(s)
E. Liu ; Cadence Design Syst. Inc., San Jose, CA, USA ; W. Kao ; E. Felt ; A. Sangiovanni-Vincentelli

This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models. A key contribution is a new algorithm for determining analog testability. Experimentally, we determined the testability and faults of a fabricated 10 bit digital-to-analog converter modeled using the analog hardware description language, Cadence-AHDL. Also, we applied the testability analysis at the circuit level using SPICE sensitivity analysis

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994