By Topic

A 85-mW, 10-bit 40-Ms/s ADC with decimated parallel architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
K. Nakamura ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; M. Hotta ; R. Carley ; D. Allstot

The design of a low-power, 10-bit 40-Ms/s ADC integrated in 0.8-μm multi-threshold CMOS is presented. This fully differential design employs a decimated parallel combination of single-bit and multi-bit per stage pipelined architectures to achieve this performance. The ADC, targeted for high resolution video terminals, dissipates 85-mW from 2.7-V supply, and occupies an area of 1.9 by 2.1-mm2

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994