A 85-mW, 10-bit 40-Ms/s ADC with decimated parallel architecture

The design of a low-power, 10-bit 40-Ms/s ADC integrated in 0.8-/spl mu/m multi-threshold CMOS is presented. This fully differential design employs a decimated parallel combination of single-bit and multi-bit per stage pipelined architectures to achieve this performance. The ADC, targeted for high resolution video terminals, dissipates 85-mW from 2.7-V supply, and occupies an area of 1.9 by 2.1-mm/sup 2/.<
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