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Transistor size optimization in layout design rule migration

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5 Author(s)
S. Kishida ; Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Y. Shibayama ; H. Tanizaki ; A. Hanami
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A new design rule migration system based on a compaction method has been developed. A transistor size optimization method has been employed in the system to achieve high performance of the circuit. The cost functions for the optimization are critical path delay time and power dissipation. The experimental work for a discrete cosign transform core processor (102 transistors) has shown the effectiveness of the migration system and the optimization method

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994