By Topic

A 1.5% jitter PLL clock generation system for a 500-MHz RISC processor

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

12 Author(s)

We have developed a clock generation system for RISC processors. The system consists of two parts of a PLL, a frequency multiplier, and a phase aligner. The multiplier can multiply the input clock frequency by 2, 4, and 8, and can accomplish a wide frequency range of output clocks, from 60 MHz to 660 MHz. Jitter is reduced to 1.5% of the output clock period by separating the clock generation system into a frequency multiplier and a phase aligner, and by developing a new differential loop filter with high sensitivity phase detection. The phase aligner reduces clock skew between the processor and peripheral LSIs. The system is fabricated with 0.4-μm CMOS triple-layer Al process technology and operated at 3.3 V

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994