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PLL timing design techniques for large-scale, high-speed, low-power, and low-cost SRAMs

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7 Author(s)

PLL timing design techniques introduced here feature (1) a word-line resetting-equalization scheme employing a clock-cycle proportional pulse, (2) a clock cyclic input buffer power-cutting scheme employing a clock-edge lookahead pulse, and (3) a super-pipelined parallel test scheme which allows the evaluation of high-speed LSIs by low-speed LSI testers. These techniques successfully contribute to the development of a 7 ns 16 Mb BiCMOS SRAM LSI

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994