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A 180 MHz multiple-registered DRAM for low-cost 2 MB/chip secondary cache

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9 Author(s)
Iwamoto, H. ; ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Watanabe, N. ; Yamazaki, A. ; Sawada, Seiji
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A Multiple-registered DRAM is described for 2 MB/chip secondary cache. 64 registers per bank of the RAM enable the data transfer from 64 dynamic memory cells to the registers simultaneously, realizing 180 MHz cache fill operation. The area increase with the architecture is only 5.4% over the conventional DRAM, which contributes to realize low-cost high-performance cache systems

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994