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GaAs HBT gate array for high performance ASICs

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9 Author(s)
Yinger, S. ; Microelectron. Technol. Center, Rockwell Int. Corp., Newbury Park, CA, USA ; Lee, F. ; Huang, R.T. ; Schneider, K.
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A high speed HBT gate array has been developed for applications requiring data rates up to 5 Gbps. Die size is 2.2 mm×2.2 mm and is packaged in a 68 pin leaded chip carrier with 20 pair of differential I/O signals. Typical power dissipation is 1 to 3 Watts. The array uses three levels of series gating enabling complex logic functions to be implemented efficiently. The top level gate delay is 40 ps for a fanout of one and 60 fF load

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994