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A multi-port RAM generator with novel memory cell for CMOS Sea-of-Gates

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4 Author(s)
Nii, K. ; Syst. LSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Maeno, H. ; Osawa, T. ; Iwade, S.

A multi-port RAM generator for 0.5 μm CMOS Sea-of-Gates (SOG) has been developed. 2-port or 3-port RAMs with flexible bit-word configurations are available. In order to operate either at a low supply voltage or at high speed, a novel memory cell circuit is proposed. In addition, a fourfold real bit line technique is adopted to improve access time. The experimental results of the test chips show that each generated RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16 b×256 w) is 4.8 ns at 3.3 V

Published in:

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Date of Conference:

1-4 May 1994