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On digit-recurrence division implementations for field programmable gate arrays

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2 Author(s)
M. E. Louie ; Dept. of Comput. Sci. Dept., California Univ., Los Angeles, CA, USA ; M. D. Ercegovac

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic-intensive programs with the benefits of custom hardware but without the high cost of custom silicon implementations. Efficient mappings are key to fast arithmetic implementations on FPGAs. A process for developing such mappings with lookup table based FPGAs is explored. The development process is illustrated with SRT division and the Xilinx XC4010 FPGA. With this mapping process a linear sequential array design that avoids the common problem of large fanout delay in the critical path is created. This approach has a cycle time that is independent of precision, yet it requires approximately the same number of logic blocks as a conventional implementation

Published in:

Computer Arithmetic, 1993. Proceedings., 11th Symposium on

Date of Conference:

29 Jun-2 Jul 1993