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An optimized compensation strategy for two-stage CMOS op amps

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2 Author(s)
G. Palmisano ; Dipartimento Elettrico Elettronico e Sistemistico, Catania Univ., Italy ; G. Palumbo

An optimized compensation strategy for two-stage Miller-compensated CMOS operational amplifiers is presented. The output conductance of the buffer which avoids the right half-plane zero is profitably used to achieve a pole-zero compensation. Indeed, thanks to a proper choice of the buffer transconductance, the compensation for the pole due to the load capacitor is reached, thus providing better frequency performance

Published in:

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications  (Volume:42 ,  Issue: 3 )