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Assembly-level reliability: a methodology for effective manufacturing of IC packages

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3 Author(s)
L. T. Nguyen ; Nat. Semicond. Corp., Santa Clara, CA, USA ; J. R. Finnell ; K. M. Singh

This paper discusses the general methodology of assembly level reliability (ALR) as part of a corporate effort at designing reliability into the whole assembly process of integrated circuit (IC) packages. Semiconductor packages with assembly-induced defects sometimes do escape detection due to a variety of reasons. Trying to eliminate this problem by approaching it piecemeal may result only in single process optimization, but does not guarantee full assembly line balancing for error-free production. ALR is a systematic 4-prong approach which uses a combination of techniques for synergistic effects. (1) Problems of immediate needs have to be addressed and contained, (2) The proper steps must then be taken to ensure that similar issues do not resurface. (3) Design-for-manufacturability principles must be applied; e.g., the design of the package can be simplified to reduce the number of assembly steps, increase throughput, and cut cost. (4) Qualification methodologies have to be revisited. Less expensive but well-characterized test chips can be introduced in lieu of actual devices. Accelerated testing with a good understanding of the failure mechanisms facilitates faster product qualification to ensure time-to-market advantage. Together with these more cost-effective qualification techniques, the proper reliability-monitoring features must be installed. Only then can the true vision of ALR be accomplished, viz, ensuring recognition, by both customers and competitors, as a Company that continuously manufactures defect-free parts

Published in:

IEEE Transactions on Reliability  (Volume:44 ,  Issue: 1 )