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A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits

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6 Author(s)
Tachibana, S. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Higuchi, H. ; Takasugi, K. ; Sasaki, K.
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The dual-sensing-latch circuit proposed here can solve the synchronization problem of the conventional wave-pipelined SRAM and the proposed source-biased self-resetting circuit reduces both the cycle and access time of cache SRAM's. A 16-kb SRAM using these circuit techniques was designed, and was fabricated with 0.25-μm CMOS technology. Simulation results indicate that this SRAM has a typical clock access time of 2.6 ns at 2.5-V supply voltage and a worst minimum cycle time of 2.6 ns

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Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 4 )