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A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers

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12 Author(s)
Ishibashi, K. ; Central Res. Lab., Hitachi Ltd., Tokyo, Japan ; Takasugi, K. ; Komiyaji, K. ; Toyoshima, H.
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A 4-Mb CMOS SRAM with 3.84 μm2 TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 4 )

Date of Publication:

Apr 1995

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