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An automatic temperature compensation of internal sense ground for subquarter micron DRAM's

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9 Author(s)
T. Ooishi ; ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan ; Y. Komiya ; K. Hamade ; M. Asakura
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This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V th), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the Vth of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (VPP is below 2 VCC). They are applicable to subquarter micron DRAM's of 256 Mb and more

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 4 )