By Topic

Optimized mapping of video applications to hardware-software for VLSI architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Gebotys, C.H. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Gebotys, R.J.

This research presents for the first time an integer optimization approach for scheduling video computations on bus-constrained VLSI architectures or on an existing VLIW processor. For many video systems a combination of processor and VLSI chip provides a low cost solution that meets given performance requirements. Thus tools for analyzing whether a video function is best implemented in hardware (VLSI) or in software (on a VLIW processor) are valuable. An optimization approach is presented which can efficiently map video computations to hardware or software. The technique maps fast (I)DCT-II applications to an existing VLIW video signal processor chip. Our research shows that the optimized mapping to VLSI architectures provides up to 66% fewer busses than previous research. This research is important for industry since the partitioning of applications into software or hardware has a significant impact on the overall cost and performance of video processing systems

Published in:

System Sciences, 1995. Proceedings of the Twenty-Eighth Hawaii International Conference on  (Volume:1 )

Date of Conference:

3-6 Jan 1995