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Current-mode building blocks for CMOS-VLSI design of chaotic neural networks

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2 Author(s)
M. Delgado-Restituto ; Centro Nacional de Microelectron., Seville, Spain ; A. Rodriguez-Vazquez

This paper presents two nonlinear CMOS current-mode circuits that implement neuron soma equations for chaotic neural networks, and another circuit to realize programmable current-mode synapse using CMOS-compatible BJTs. They have been fabricated in a double-metal, single-poly 1.6 μm CMOS technology and their measured performance reached the expected function and specifications. The neuron soma circuits use a novel, highly accurate CMOS circuit strategy to realize piecewise-linear characteristics in current-mode domain. Their prototypes obtain reduced area and low voltage power supply (down to 3 V) with clock frequency of 500 kHz. As regard to the synapse circuit, it obtains large linearity and continuous, linear, weight adjustment by exploitation of the exponential-law operation of CMOS-BJTs. The full accordance observed between theory and measurements supports the development of future analog VLSI chaotic neural networks to emulate biological systems and advanced computation

Published in:

Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on  (Volume:6 )

Date of Conference:

27 Jun- 2 Jul 1994