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A unified bit-parallel arithmetic processor using redundant binary representation

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1 Author(s)
Sau-Gee Chen ; Microelectron. & Inf. Sci. Res. Center, Nat. Chiao Tung Univ., Hsinchu, Taiwan

An addition rule for signed-digit representation (SDR), generalized from the addition rule of redundant binary representation, is proposed which is free from carry-propagation. The MSD (most significant digit)-first multiplication operation is easily devised by incorporating hardware redundancy with the redundancy in this addition rule. By combining all the MSD-first arithmetic operations, a unified arithmetic processor is obtained which can perform division, multiplication, and square-root operations. This unified processor is similar in structure to an array multiplier. It provides three advantages over the conventional arithmetic unit: (1) higher speed, (2) more functional capability, and (3) better area utilization. It is also suitable for VLSI implementation.<>

Published in:

Computers and Communications, 1989. Conference Proceedings., Eighth Annual International Phoenix Conference on

Date of Conference:

22-24 March 1989