VLSI implementation of a CORDIC SVD processor

The design and custom CMOS VLSI implementation of a CORDIC SVD (singular-value decomposition) processor is presented. Special-purpose parallel processor arrays have many important applications in real-time signal processing. The processor architecture is reviewed and the current CORDIC Z-control and X,Y data path chips are described. Current work includes the expansion of the 10-bit CORDIC Z-control chip to a 20-bit design to complement the CORDIC X,Y data path design. The hierarchical design methodology will lead next to a full CORDIC processor followed by a complete CORDIC SVD processor and array