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A planar electrode array in standard CMOS technology

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2 Author(s)
A. E. Hubbard ; Coll. of Eng., Boston Univ., MA, USA ; B. P. Houghton

The development of a cheap, useful electrode array chip for scientific and medical applications is discussed. The chip is targeted for an experimental situation in which the neurological structure being studied could lie on or against the chip surface. The authors report on the minimum-sized electrode array which can reliably be built using standard CMOS fabrication techniques. The data suggest that the minimum-sized electrode array may be constructed using two-lambda glass cuts centered over six-lambda metal 2 regions separated by at least two lambda. A 64-electrode, multiplexed, recording-array chip, which is currently in fabrication, is also shown

Published in:

University/Government/Industry Microelectronics Symposium, 1989. Proceedings., Eighth

Date of Conference:

12-14 Jun 1989