Cart (Loading....) | Create Account
Close category search window
 

Robust VLSI circuit simulation techniques based on overlapped waveform relaxation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Fang, W. ; Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA ; Mokari, M.E. ; Smart, D.

High-performance mainframe computers are commonly implemented using bipolar VLSI technologies. The simulation of such circuits is very time-consuming using traditional direct methods, as in SPICE. Relaxation-based methods such as waveform relaxation (WR) have been used to speed up the simulation of MOS circuits, but they have not been as effective for bipolar circuits because of the strong coupling between logic gates. In this paper, a fast, robust overlapped waveform relaxation (OWR) algorithm is presented. OWR is effective for bipolar circuits because it uses an overlapped partitioning strategy to overcome the effect of strong coupling on convergence speed. To demonstrate the effectiveness of this algorithm, simulation results are presented for combinational and sequential digital bipolar circuits as well as analog bipolar circuits. From the simulation results, it can be concluded that the speed advantage of OWR compared to the direct method increases with circuit size. The OWR algorithm is more robust than standard WR; it converges in cases where WR diverges or converges too slowly. OWR is about two times faster than WR for tightly coupled bipolar circuits

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:14 ,  Issue: 4 )

Date of Publication:

Apr 1995

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.