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A fast VLSI-efficient self-routing permutation network

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2 Author(s)
Cam, H. ; Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia ; Fortes, J.A.B.

A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2×4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has O(log2 N) gate-delay and uses O(N2) VLSI-area, where N is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date

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Computers, IEEE Transactions on  (Volume:44 ,  Issue: 3 )