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Thermal modeling and experimental characterization of the C4/surface-mount-array interconnect technologies

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1 Author(s)
G. B. Kromann ; Adv. Packaging Technol., Microprocessor Memory & Technol. Group, Motorola Inc., Austin, TX, USA

This paper presents various thermal management options available for controlled collapse chip connection (C4) die attached to a ceramic surface mount array (SMA) substrate, as they apply to low end/midrange computer products. The Motorola 88110 RISC microprocessor was used as a thermal test vehicle to verify theoretical models, for a limited set of boundary conditions. A thermal test board was designed to accommodate the 25 mm substrate and its use will be discussed. The focus is the internal package resistance and the effects of parameters such as: the 64 bumps, the thermal paste, and the thermal paste thickness, However, the die junction-to-ambient resistance is presented for attached commercially-available heat sinks convectively cooled (to 4 m/s) for typical workstation computer-systems operational constraints

Published in:

IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A  (Volume:18 ,  Issue: 1 )