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Long-term bias temperature reliability of P+ polysilicon gated FET devices

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4 Author(s)
Abadeer, Wagdi W. ; IBM Microelectron., Essex Junction, VT, USA ; Tonti, W.R. ; Hansch, W.E. ; Schwalke, U.

An instability was found to be associated with +BT stress for P + poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N+ poly-gated devices (NNMOS and NPMOS). The instability with the P+ poly-gated devices, which is a decrease in threshold voltage (Vt) and an increase in interface state density (Dit), was significantly reduced following N2 annealing at 400°C. It is shown that adequate reliability for P+ poly-gated devices can be achieved for VLSI technologies

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Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 2 )