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Impact of switch architectures on the performance of multistage interconnection networks

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2 Author(s)
Zhou, B. ; Dept. of Comput. Sci. & Eng., La Trobe Univ., Bundoora, Vic., Australia ; Atiquzzaman, M.

Switching elements in interconnection networks for highly parallel shared memory computer systems may be implemented with different internal buffer structures. A multistage interconnection network (MIN) consist of several stages of small crossbar switching elements (SEs). The aim of this paper is to study the performance of a multibuffered MIN with different SEs architecture, in the presence of uniform and nonuniform traffic. For the purpose of comparison, the throughput and the network delay have been used as the performance measures

Published in:

TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994

Date of Conference:

22-26 Aug 1994