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Simulation and performance evaluation of parallel architecture based on i860 nodes: SapePar-i860

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4 Author(s)
Pandlan, A. ; Dept. of Electr. Eng., Indian Inst. of Sci., Bangalore, India ; Parthasarathy, K. ; Sridhar, M.K. ; Gowda, K.C.

SapePar-i860 is an execution driven “Simulator and Performance Evaluator for i860 based Parallel Architecture”. The simulator has various inputs like the primary cache size, primary cache type, secondary cache size, secondary cache type, secondary cache replacement policy, number of processors, interconnection between the processors, communication path from each processor to other processors, type of communication and bandwidth of communication channels. The simulator gets configured automatically according to the inputs and generates log files. The performance analyzer generates statistics of the run based on these log files. The statistics includes cache hit ratio of primary cache, cache hit ratio of secondary cache, Complete Communication Ratio (CCRi) of each processor, the Compute Communication Ratio (CCR6) of overall system, efficiency of each processor and efficiency of overall system. This also computes the speedup, execution time in terms of clock ticks

Published in:

TENCON '94. IEEE Region 10's Ninth Annual International Conference. Theme: Frontiers of Computer Technology. Proceedings of 1994

Date of Conference:

22-26 Aug 1994