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A fast algorithm for computing a histogram on reconfigurable mesh

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3 Author(s)
Ju-Wook Jang ; Samsung Electron. Co. Ltd., Seoul, South Korea ; Heonchul Park ; V. K. Prasanna

The reconfigurable mesh captures salient features from a variety of sources, including the content addressable array parallel processor, the CHiP, the polymorphic-torus network and the bus automaton. It consists of an array of processors interconnected by a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns between the processors. In this paper, we present a fast algorithm for computing the histogram of an N×N image with h grey levels in O(min{√h+log*(N/h),N}) time on an N×N reconfigurable mesh assuming each PE has a constant amount of local memory. This algorithm runs on the PARBUS and MRN/LRN models. In addition, histogram modification can be performed in O(√h) time on the same model. A variant of out algorithm runs in O(min{√h+log log(N/h),N}) time on an N×N RMESH in which each PE has constant storage. This result improves the known time and memory bounds for histogramming on the RMESH model

Published in:

IEEE Transactions on Pattern Analysis and Machine Intelligence  (Volume:17 ,  Issue: 2 )