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Efficient image processing algorithms on the scan line array processor

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2 Author(s)
D. Helman ; Dept. of Electr. Eng., Maryland Univ., College Park, MD, USA ; J. JaJa

Develops efficient algorithms for low and intermediate level image processing on the scan line array processor, a SIMD machine consisting of a linear array of cells that processes images in a scan line fashion. For low level processing, the authors present algorithms for block DFT, block DCT, convolution, template matching, shrinking, and expanding which run in real-time. By real-time, the authors mean that, if the required processing is based on neighborhoods of size m×m, then the output lines are generated at a rate of O(m) operations per line and a latency of O(m) scan lines, which is the best that can be achieved on this model. The authors also develop an algorithm for median filtering which runs in almost real-time at a cost of O(m log m) time per scan line and a latency of [m/2] scan lines. For intermediate level processing, the authors present optimal algorithms for translation, histogram computation, scaling, and rotation. The authors also develop efficient algorithms for labelling the connected components and determining the convex hulls of multiple figures which run in O(n log n) and O(n log2n) time, respectively. The latter algorithms are significantly simpler and easier to implement than those already reported in the literature for linear arrays

Published in:

IEEE Transactions on Pattern Analysis and Machine Intelligence  (Volume:17 ,  Issue: 1 )