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A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

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17 Author(s)
J. M. Sung ; AT&T Bell Labs., Holmdel, NJ, USA ; T. -Y. Chiu ; K. Lau ; T. M. Liu
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A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved fl and fmax for npn bipolar (Ae=1×2 μm2) of 23 GHz and 24 GHz at Vce=3 V, respectively, with BVceo⩾5.5 volts, and βVA product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (Ae=1×2 μm2 ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, Leff=0.6 μm; Vth,nch =0.45 V; Vth,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate Leff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW

Published in:

IEEE Transactions on Electron Devices  (Volume:42 ,  Issue: 3 )