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High speed submicron BiCMOS memory

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3 Author(s)
Takada, M. ; Syst. ULSI Res. Lab., NEC Corp., Kanagawa, Japan ; Nakamura, K. ; Yamazaki, T.

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM's. Future prospects for submicron BiCMOS memories are also forecasted

Published in:

Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 3 )