By Topic

Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Iinuma, T. ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; Itoh, N. ; Nakajima, H. ; Inou, K.
more authors

Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing fT values. In this paper, we demonstrate a device with sub-20 ps tpd values even at fT=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce CCB, 2) a low-concentration collector design to reduce CCB, 3) NiSi-salicided base and emitter electrodes to reduce RB, and 4) a shallow base formed by double diffusion technology for relatively high fT with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V

Published in:

Electron Devices, IEEE Transactions on  (Volume:42 ,  Issue: 3 )