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Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture

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9 Author(s)
T. Iinuma ; ULSI Res. Center, Toshiba Corp., Kawasaki, Japan ; N. Itoh ; H. Nakajima ; K. Inou
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Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing fT values. In this paper, we demonstrate a device with sub-20 ps tpd values even at fT=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce CCB, 2) a low-concentration collector design to reduce CCB, 3) NiSi-salicided base and emitter electrodes to reduce RB, and 4) a shallow base formed by double diffusion technology for relatively high fT with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V

Published in:

IEEE Transactions on Electron Devices  (Volume:42 ,  Issue: 3 )