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An automaton model for scheduling constraints in synchronous machines

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3 Author(s)
A. Takach ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; W. Wolf ; M. Lesser

We present a finite-state model for scheduling constraints in digital system design. We define a two-level hierarchy of finite-state machines: a behavior FSM's input and output events are partially ordered in time; a register-transfer FSM is a traditional FSM whose inputs and outputs are totally ordered in time. Explicit modeling of scheduling constraints is useful for both high-level synthesis and verification-we can explicitly search the space of register-transfer FSM's which implement a desired schedule. State-based models for scheduling are particularly important in the design of control-dominated systems. This paper describes the BFSM I model, describes several important operations and algorithms on BFSM's and networks of communicating BFSM's, and illustrates the use of BFSM's in high-level synthesis.<>

Published in:

IEEE Transactions on Computers  (Volume:44 ,  Issue: 1 )