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Routing in a three-dimensional chip

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2 Author(s)
Chao Chi Tong ; Center for Adv. Food Technol., Rutgers Univ., New Brunswick, NJ, USA ; Chuan-lin Wu

As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 μm, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation

Published in:

Computers, IEEE Transactions on  (Volume:44 ,  Issue: 1 )