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A remark on “Reducing iteration time when result digit is zero for radix-2 SRT division and square root with redundant remainders”

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2 Author(s)
Montuschi, P. ; Dipartimento di Autom. e Inf., Politecnico di Torino, Italy ; Ciminiera, L.

In a previous paper by P. Montuschi and L. Ciminiera (ibid., vol. 42, no.2 p239-246, Feb 1993), an architecture for shared radix 2 division and square root has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteristics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, which has the benefit to further reduce the computation delay with respect to the time estimated in that work

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Computers, IEEE Transactions on  (Volume:44 ,  Issue: 1 )