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Hierarchical simulation of high speed digital interconnects using a packaging simulator

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3 Author(s)
Basel, M.S. ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; Steer, M.B. ; Franzon, P.D.

A hierarchical strategy is presented which permits the tradeoff of modeling and simulation accuracy with simulation speed in the simulation of high speed signals on interconnects in multichip modules and printed circuit boards. Using a point modeling paradigm for discontinuities and impulse response thresholding a smooth transition is achieved between delay modeling and full circuit simulation

Published in:

Electronic Components and Technology Conference, 1994. Proceedings., 44th

Date of Conference:

1-4 May 1994