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Test generation and fault simulation algorithms for sequential circuits with embedded RAMs

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2 Author(s)
Chakraborty, T.J. ; AT&T Bell Labs., Princeton, NJ, USA ; Agrawal, V.D.

In this paper, novel algorithms are given for test generation and fault simulation for sequential circuits with embedded RAMs. Stuck-at faults are propagated through these RAMs that are represented as functional models. While only faults on the input and output data lines are targeted for test generation, all faults of the RAM model, including the faults on the address and read/write lines are, simulated. A dynamic and very efficient memory management scheme is proposed to store the faulty values in the embedded RAMs during fault simulation. Although the test generation algorithm is not a complete algorithm, most address and read/write faults are detected during fault simulation of test vectors generated for other faults. Results indicate that high fault coverage can be achieved for practical circuits. A proposed design for testability requires scanning of only the address and read/write lines of RAMs

Published in:

Test Symposium, 1994., Proceedings of the Third Asian

Date of Conference:

15-17 Nov 1994

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