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Mapping iterative algorithms onto processor arrays by the use of Petri Net models

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3 Author(s)
Karagianni, K.E. ; Dept. of Electr. Eng., Patras Univ., Greece ; Kyriakis-Bitzaros, E.D. ; Stouraitis, T.

In this paper, Petri Nets (PNs) are used for deriving efficient mapping transformations of a wide class of algorithms to processor arrays. In the proposed methodology, given an algorithm and the interconnections of the processor array, two PNs are constructed: one that is related to the algorithm and one that is related to the processor array. The former PN models the execution of the algorithm and differs drastically from the common data-flow methods. Based on properties of PNs and on the reachability tree analysis technique, a theorem is given, through which the two PN model suggest all possible ways of implementing the algorithm by the processor array

Published in:

Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on

Date of Conference:

2-6 May 1994

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