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High performance modular arithmetic using an RNS based chipset

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3 Author(s)
J. Schwemmlein ; Inst. for Appl. Inf. Process. & Commun., Graz Univ. of Technol., Austria ; R. Posch ; K. C. Posch

This paper presents a distributed computing architecture capable of performing long integer arithmetic. Special attention is given to module multiplication. To avoid carry propagation delays, the design makes use of RNS arithmetic. In RNS, additions and multiplications can be computed in parallel. Several VLSI processing elements are grouped together, each holding one RNS digit. These devices exchange information on a data bus. Instructions sequenced by an additional chip control synchronized execution. Thus, the system can be seen as a SIMD architecture performing modular arithmetic. Some instructions differ from a pure SIMD concept. The system is tuned for special purpose computations. As a sample application suitable for the presented chip set, an RSA like enciphering method (MRSA) is shown

Published in:

Massively Parallel Computing Systems, 1994., Proceedings of the First International Conference on

Date of Conference:

2-6 May 1994