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Implementation of a priority forwarding router chip for real-time interconnection networks

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5 Author(s)
Toda, K. ; Electrotech. Lab., Tsukuba, Japan ; Nishida, K. ; Takahashi, E. ; Michell, N.
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A single-chip VLSI implementation of a 4 by 4 prioritized router for multistage real-time interconnection networks is presented. The chip employs packet switching and facilitates 32-bit priority arbitration by means of a priority forwarding scheme that prevents priority inversion and which provides accurate priority control in a network. The packets are of fixed size, having three 38-bit segments: a header and two bodies. Each input port has an 8-packet priority queue for simultaneous input and output, enabling virtual cut-through routing. The chip is pipelined with a 25-ns pitch and reduces the number of stages to two by overlapping the arbitration and priority queue stages. Hence, its data transmission rate is 190 MByte/s per port. The end-to-end delay of an s-stage network is 25×(2s+1) ns

Published in:

Parallel and Distributed Real-Time Systems, 1994. Proceedings of the Second Workshop on

Date of Conference:

28-29 Apr 1994