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High speed electrical characterization and simulation of a pin grid array package

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4 Author(s)
Goodman, T.W. ; Div. of Inf. & Telecommun. LSI, Sony Semicond. Co., Atsugi, Japan ; Fujita, H. ; Murakami, Y. ; Murphy, A.T.

A 181 pin Pin Grid Array (PGA) was characterized using time and frequency domain techniques to identify major sources of signal degradation. The pins, as well as a layer of plating lines that was included for electroplating the exterior metal surfaces, were found to have a deleterious effect on the signal transmission within the package. In addition, a ground delay resulting from the separation of the signal pin and its nearest ground pin was seen to cause significant degradation in signal lines whose pin was far from a ground I/O. For signal lines that are geometrically equivalent due to package symmetry, this effect was seen to increase with increasing signal/nearest ground pin distance, resulting in as much as a 79% increase in the package risetime in some lines. These effects were simulated using a model whose elements were based on actual physical structures, within the package and whose parameters were derived from experimental measurements

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Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:18 ,  Issue: 1 )