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C-testable design techniques for iterative logic arrays

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3 Author(s)
Shyue-Kung Lu ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Jen-Chuan Wang ; Cheng-Wen Wu

A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table augmentation approach. We propose an output-assignment algorithm for minimizing the hardware overhead. We give a CMOS systolic array multiplier as an example, and show that an overhead of no more than 5.88% is sufficient to make it C-testable, i.e., 100% single cell-fault testable with only 18 test patterns regardless of the word length of the multiplier. Our technique guarantees that the test set is easy to generate. Its corresponding built-in-self-test structures are also very simple.<>

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:3 ,  Issue: 1 )