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On general zero-skew clock net construction

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2 Author(s)
Nan-Chi Chou ; Quickturn Design Syst., Mountain View, CA, USA ; Chung-Kuan Cheng

We propose a simulated annealing based zero-skew clock net construction algorithm that works in any routing spaces, from Manhattan to Euclidean, with the added flexibility of optimizing either the wire length or the propagation delay. We first devise an O(log n) tree grafting perturbation function to construct a zero-skew clock tree under the Elmore delay model. This tree grafting scheme is able to explore the entire solution space asymptotically. A Gauss-Seidel iteration procedure is then applied to optimize the Steiner point positions. Experimental results have shown that our algorithm can achieve substantial delay reduction and encouraging wire length minimization compared to previous works.<>

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:3 ,  Issue: 1 )