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Parallel algorithms and VLSI architectures for stack filtering using Fibonacci p-codes

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5 Author(s)
Gevorkian, D.Z. ; Inst. for Problems of Inf. & Autom., Acad. of Sci., Yerevan, Armenia ; Egiazarian, K.O. ; Agaian, S.S. ; Astola, J.T.
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A parallel decompositional algorithm and VLSI architecture is proposed for computation of the output of a stack filter over a single window of input samples using Fibonacci p-codes. For a subclass of positive Boolean functions, a more efficient parallel algorithm and VLSI architecture for running stack filtering is also presented. The area-time complexities of the proposed designs are estimated

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Signal Processing, IEEE Transactions on  (Volume:43 ,  Issue: 1 )