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Timing models for gallium arsenide direct-coupled FET logic circuits

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2 Author(s)
A. I. Kayssi ; Dept. of Electr. Eng., American Univ. of Beirut, Lebanon ; K. A. Sakallah

In this paper we derive delay and transition time macromodels for GaAs DCFL logic gates. The macromodels are derived by a systematic application of dimensional analysis aimed at finding suitable minimal functional forms that capture the effects of all relevant parameters. The process is illustrated through a detailed step-by-step account of the macromodel development for DCFL inverters. Based on different modeling approximations, one- and two-argument macromodel functions are derived and compared. The inverter macromodel is then used as a basis for developing timing macromodels for superbuffers and NOR gates. The NOR gate macromodels account for the simultaneous and near-simultaneous switching of two inputs, with an extension to multiple inputs

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:14 ,  Issue: 3 )