Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
Wen-Ben Jone ; Dept. of Comput. Sci., Nat. Chung-Cheng Univ., Chiayi, Taiwan ; Papachristou, Christos A.

In this paper, we present a circuit partitioning and test pattern generation technique for pseudo-exhaustive built-in self-testing of VLSI circuits. The circuit partitioning process divides a given circuit into a set of subcircuits which can be exhaustively tested, while the test pattern generation process generates reduced exhaustive test patterns for each subcircuit using a linear feedback shift register (LFSR). In conventional approaches, these two problems are considered separately. However, in this paper, both problems are considered and solved in the same phase. A graph theoretic model of VLSI circuits is proposed. Based on this model, a circuit partitioning algorithm using the concept of minimum vertex cut is devised to partition the circuit into a set of exhaustively testable subcircuits with restricted hardware overhead. Each time a subcircuit is generated by the partitioning algorithm, the test pattern generation problem is considered. A new algorithm, based on the subcircuit modification technique, is proposed with the objective of generating reduced exhaustive test patterns of limited length (e.g., ⩽220) using LFSR's, for each of the subcircuits. This task is embedded in the circuit partitioning process itself, leading to an efficient and well-coordinated solution. Experiments using ISCAS benchmark circuit simulation have been conducted. The results demonstrate that the proposed method is very good

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:14 ,  Issue: 3 )