Referenced Items are not available for this document.
A yield model has been developed and validated for use in optimizing VLSI floorplanning in next generation products. The model successfully predicts yields and costs on a variety of products in CMOS, bipolar, and BiCMOS process flows from low cost DIP's and QFP's to more complex PGAs and flip chip package solutions. This paper discusses how the model was developed for use in evaluating the viability of next generation VLSI solutions. The model takes into account variables such as layout sensitivity, circuit redundancy, and learning curves in wafer, assembly, and test processing in determining the total manufacturing cost
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:30
,
Issue:
3
)
Date of Publication: Mar 1995
- Page(s):
- 286 - 294
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4907137
- Digital Object Identifier :
- 10.1109/4.364443
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Mar 1995
- Sponsored by :
- IEEE Solid-State Circuits Society
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