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An array processor for general purpose digital image compression

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5 Author(s)
R. B. Yates ; Dept. of Electron. & Electr. Eng., Sheffield Univ., UK ; N. A. Thacker ; S. J. Evans ; S. N. Walker
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A new VLSI processor (DIP chip) for image compression is presented which combines principles of multipipeline and array processing. The device is not specific to any one image compression algorithm and can be regarded as a general purpose processor. The chip has been implemented using a CMOS 1.0-μm process on a 14.4×13.5-mm2 die. An internal clock frequency of 40 MHz results in 1.2×109 operations/s on 8-bit data. Solutions to problems associated with the large bandwidth required, for both image data and instruction streams, is the main aim of the paper. The necessary problem of increasing the array clock frequency relative to the input/output clock frequency without the need for a large on-chip instruction cache or fast external clock speeds is also addressed

Published in:

IEEE Journal of Solid-State Circuits  (Volume:30 ,  Issue: 3 )