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Improved switched-current (SI) bilinear integrator circuit

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2 Author(s)
Psychalinos, C. ; Dept. of Electr. Eng., Patras Univ., Greece ; Goutis, C.E.

A bilinear SI integrator circuit with a reduced number of current mirrors is presented. The realisation of the circuit is based on the modification of the corresponding block diagram, to eliminate the required current inversions without delay. The resulting circuit has improved sensitivity performance to current mirror ratio variations

Published in:

Electronics Letters  (Volume:31 ,  Issue: 1 )