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Paralleled hardware annealing in multilevel Hopfield neural networks for optimal solutions

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4 Author(s)
Sa Hyun Bang ; Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Chen, O.T.-C. ; Chang, J.C.-F. ; Sheu, B.J.

In a multilevel neural network, the output of each neuron is to produce a multi-bit representation. Therefore, the total network size can be significantly smaller than a conventional network. The reduction in network size is a highly desirable feature in large-scale applications. The procedure for applying hardware annealing by continuously changing the neuron gain from a low value to a certain high value, to reach the globally optimal solution is described. Several simulation results are also presented. The hardware annealing technique can be applied to the neurons in a parallel format, and is much faster than the simulated annealing method on digital computers

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:42 ,  Issue: 1 )

Date of Publication:

Jan 1995

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