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Parallel constant-time connectivity algorithms on a reconfigurable network of processors

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1 Author(s)
Alnuweiri, H.M. ; Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada

This short note presents constant-time algorithms for labeling the connected components of an image on a network of processors with a wide reconfigurable bus. The algorithms are based on a processor indexing scheme which employs constant-weight codes. The use of such codes enables identifying a single representative processor for each component in a constant number of steps. The proposed algorithms can label an N×N image in O(1) time using N2 processors, which is optimal. Furthermore, the proposed techniques lead to an O(logN/loglogN)-time image labeling algorithm on a network of N2 processors with a reconfigurable bus of width log N bits. It is shown that these techniques on be applied to labeling an undirected N-vertex graph represented by an adjacency matrix

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Parallel and Distributed Systems, IEEE Transactions on  (Volume:6 ,  Issue: 1 )